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PIC18F8720/8620/6720/6620
PIC18F8720/8620/6720/6620 Rev. A4 Silicon/Data Sheet Errata
The PIC18F8720/8620/6720/6620 parts you have received conform functionally to the Device Data Sheet (DS39609B), except for the anomalies described below. All of the issues listed here will be addressed in future revisions of the PIC18F8720/8620/6720/6620 silicon. The following silicon errata apply only to PIC18F8720/8620/6720/6620 devices with these Device/Revision IDs: Part Number PIC18F6620 PIC18F6720 PIC18F8620 PIC18F8720 Device ID 00 0110 011 00 0110 001 00 0110 010 00 0110 000 Revision ID 00100 00100 00100 00100
2. Module: External Memory Interface (PIC18F8620 only)
In Extended Microcontroller mode, or Microprocessor mode, the external memory interface is inactive from 20000h to 2FFFFh. ALE and WRL signals are inactive between 20000h and 2FFFFh. Work around Shift RAM space to 30000h and above, or as an alternate solution, the PIC18F8720 device can be used. This issue will be resolved in a future version of silicon. Date Codes that pertain to this issue: All engineering and production devices.
The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in the device's configuration space. They are shown in hexadecimal in the format "DEVID2 DEVID1".
3. Module: I/O Ports (Parallel Slave Port)
While operating in Parallel Slave Port mode, the OBF bit (PSPCON<6>) is supposed to be set when a byte is written to either PORTD or LATD. It has been noted that OBF may not be correctly set when a byte is written to LATD. If the byte is written to PORTD, then the OBF bit is set correctly. Work around To ensure the OBF bit is set correctly, write to PORTD rather than LATD. Date Codes that pertain to this issue: All engineering and production devices.
1. Module: Core (Program Memory Space)
Performing table read operations above the user program memory space (addresses over 1FFFFFh) may yield erroneous results at the extreme low end of the device's rated temperature range (-40C). This applies specifically to addresses above 1FFFFFh, including the user ID locations (200000h-200007h), the configuration bytes (300000h-30000Dh) and the device ID locations (3FFFFEh and 3FFFFFh). User program memory is unaffected. Work around Two possible work arounds are presented. Other solutions may exist. 1. Do not perform table read operations on areas above the user memory space at -40C. 2. Insert NOP instructions (specifically, literal FFFFh) around any table read instructions. The suggested optimal number is 4 instructions before and 8 instructions after each table read. This may vary depending upon the particular application and should be optimized by the user. Date Codes that pertain to this issue: All engineering and production devices.
4. Module: A/D (External Voltage Reference) and Comparator Voltage Reference
When the external voltage reference, VREF-, is selected for use with either the A/D or comparator voltage reference, AVSS is connected to VREF- in the comparator module. If VREF- is a voltage other than AVSS (which must be tied externally to VSS), excessive current will flow into the VREF- pin. Work around If external VREF- is used with a voltage other than 0V, enable the comparator voltage reference by setting the CVREN bit in the CVRCON register. This disconnects VREF- and AVSS within the comparator module. Date Codes that pertain to this issue: All engineering and production devices.
(c) 2005 Microchip Technology Inc.
DS80172C-page 1
PIC18F8720/8620/6720/6620
5. Module: DAW Instruction
The DAW instruction may improperly clear the Carry bit (STATUS<0>) when executed. Work around Test the Carry bit state before executing the DAW instruction. If the Carry bit is set, increment the next higher byte to be added, using an instruction such as INCFSZ (this instruction does not affect any Status flags and will not overflow a BCD nibble). After the DAW instruction has been executed, process the Carry bit normally (see Example 1).
7. Module: MSSP (All I2CTM and SPITM Modes)
The Buffer Full (BF) flag bit of the SSPSTAT register (SSPSTAT<0>) may be inadvertently cleared even when the SSPBUF register has not been read. This will occur only when the following two conditions occur simultaneously: * The four Least Significant bits of the BSR register are equal to 0Fh (BSR<3:0> = 1111); and * Any instruction that contains C9h in its 8 Least Significant bits (i.e., register file addresses, literal data, address offsets, etc.) is executed. Work around
EXAMPLE 1:
MOVLW ADDLW BTFSC INCFSZ DAW BTFSC INCFSZ 0x80 0x80 STATUS,C byte2 STATUS,C byte2
PROCESSING THE CARRY BIT DURING BCD ADDITIONS
; .80 (BCD) ; .80 (BCD) ; test C ; inc next higher LSB ; test C ; inc next higher LSB
All work arounds will involve setting the contents of BSR<3:0> to some value other than 0Fh. In addition to those proposed below, other solutions may exist. 1. When developing or modifying code, keep these guidelines in mind: * Assign 12-bit addresses to all variables. This allows the assembler to know when Access Banking can be used. * Do not set the BSR to point to Bank 15 (BSR = 0Fh). * Allow the assembler to manipulate the access bit present in most instructions. Accessing the SFRs in Bank 15 will be done through the Access Bank. Continue to use the BSR to select all GPR Banks. 2. If accessing a part of Bank 15 is required and the use of Access Banking is not possible, consider using indirect addressing. 3. If pointing the BSR to Bank 15 is unavoidable, review the absolute file listing. Verify that no instructions contain C9h in the 8 Least Significant bits while the BSR points to Bank 15 (BSR = 0Fh). Date Codes that pertain to this issue: All engineering and production devices.
This is repeated for each DAW instruction
Date Codes that pertain to this issue: All engineering and production devices.
6. Module: External Memory Interface (PIC18F8720 and PIC18F8620 only)
When performing writes on the external memory interface, a short glitch is present on the LB and UB lines. The length of the glitch is proportional to FOSC and also may vary with process, voltage and temperature. The glitch occurs well before the WRH line is asserted and no adverse affect on the operation of the external memory interface has been observed. Work around None Date Codes that pertain to this issue: All engineering and production devices.
DS80172C-page 2
(c) 2005 Microchip Technology Inc.
PIC18F8720/8620/6720/6620
8. Module: Reset
It has been observed that in certain Reset conditions, including power-up, the first GOTO instruction at address 0x0000 may not be executed. This occurrence is rare and affects very few applications. To determine if your system is affected, test a statistically significant number of applications across the operating temperature, voltage and frequency ranges of the application. Affected systems will repeatably fail normal testing. Systems not affected will continue to not be affected over time. Work around Insert a NOP instruction at address 0x0000. Date Codes that pertain to this issue: All engineering and production devices.
(c) 2005 Microchip Technology Inc.
DS80172C-page 3
PIC18F8720/8620/6720/6620
Clarifications/Corrections to the Data Sheet:
In the Device Data Sheet (DS39609B), the following clarifications and corrections should be noted.
1. Module: Voltage-Frequency Graph
In Section 26.0 "Electrical Characteristics", the following figure has been updated to clarify the voltage frequency for Extended devices.
FIGURE 26-3:
PIC18F6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V 5.0V PIC18FX620/X720 4.2V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
16 MHz (Extended)
25 MHz (Industrial)
Frequency
DS80172C-page 4
(c) 2005 Microchip Technology Inc.
PIC18F8720/8620/6720/6620
2. Module: Timing Diagrams and Specifications
Table 26-6: External Clock Timing Requirements for PIC18FX620/X720 devices (page 322) has been revised (changes and additions are shown in bold text).
TABLE 26-6:
Param No. 1A Symbol FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKI Frequency(1) Min DC DC Oscillator Frequency(1) DC 0.1 4 4 4 4 5 Max 25 16 4 4 25 16 6.25 4 33 -- -- -- 10,000 250 250 250 250 200 Units MHz MHz MHz MHz MHz MHz MHz MHz kHz ns ns ns ns ns ns ns ns s Conditions EC, ECIO oscillator, PIC18FX620/X720 (Industrial) EC, ECIO oscillator, PIC18FX620/X720 (Extended) RC oscillator XT oscillator HS oscillator (Industrial) HS oscillator (Extended) HS + PLL oscillator, PIC18FX620/X720 (Industrial) HS + PLL oscillator, PIC18FX620/X720 (Extended) LP Oscillator mode EC, ECIO oscillator, PIC18FX620/X720 (Industrial) EC, ECIO oscillator, PIC18FX620/X720 (Extended) RC oscillator XT oscillator HS oscillator (Industrial) HS oscillator (Extended) HS + PLL oscillator, PIC18FX620/X720 (Industrial) HS + PLL oscillator, PIC18FX620/X720 (Extended) LP Oscillator mode
1
TOSC
External CLKI Period(1)
40 62.5
Oscillator Period(1)
250 250 40 62.5 160 250 30
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
3. Module: CCP
In Section 23.3.1 "Wake-up From Sleep", the list of peripheral interrupts which can wake the device from Sleep has been updated. From the list of 11 events, item 4 has been clarified and item 5 has been removed. The list now reads as follows: 1. PSP read or write. 2. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. TMR3 interrupt. Timer3 must be operating as an asynchronous counter.
4. CCP Capture mode interrupt (Capture will not occur). 5. MSSP (Start/Stop) bit detect interrupt. 6. MSSP transmit or receive in Slave mode (SPI/I2C). 7. USART RX or TX (Synchronous Slave mode). 8. A/D conversion (when A/D clock source is RC). 9. EEPROM write operation complete. 10. LVD interrupt.
(c) 2005 Microchip Technology Inc.
DS80172C-page 5
PIC18F8720/8620/6720/6620
4. Module: Voltage Reference Specifications
In Table 26-2: Voltage Reference Specifications (page 317), parameter D311, VRAA, should be replaced with the following:
TABLE 26-2:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. D311 Note 1: Sym VRAA Characteristics Absolute Accuracy Min -- Typ -- Max 1/2 Units LSb Comments
Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111'.
5. Module: Memory Programming Requirements
In Table 26-4: Memory Programming Requirements (page 319), specification D124 (TREF) and Note 4 have been added:
TABLE 26-4:
MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Data EEPROM Memory Min Typ Max Units Conditions
DC Characteristics Param No.
Sym
D124
TREF
Total Number of Erase/Write Cycles before Refresh (Note 4)
1M 100K
10M 1M
-- --
E/W -40C to +85C E/W -40C to +125C
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: The pin may be kept in this range at times other than programming, but it is not recommended. 3: Retention time is valid, provided no other specifications are violated. 4: Refer to Section 7.8 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance.
DS80172C-page 6
(c) 2005 Microchip Technology Inc.
PIC18F8720/8620/6720/6620
6. Module: DC Characteristics
In Section 26-3 "DC Characteristics" (page 315), the specifications for VIL and VIH have been clarified and now read as follows (changes and additions are shown in bold text):
26.3
DC Characteristics PIC18F8720/8620/6720/6620 (Industrial, Extended) PIC18LF6620/8620/6720/8720 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Input Low Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 (in XT, HS and LP modes) and T1OSI OSC1 OSC1 OSC1 T13CKI VIH Input High Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer RC3 and RC4 MCLR, OSC1 (EC mode) OSC1 and T1OSI OSC1 OSC1 OSC1 OSC1 T13CKI 0.25 VDD + 0.8V 2.0 0.8 VDD 0.7 VDD 0.8 VDD 1.6 0.7 VDD 0.8 VDD 0.9 VDD 1.6 1.6 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD V V V V V V V V V V V LP, XT, HS, HSPLL modes(1) HS, HSPLL modes EC mode RC mode(1) XT, LP modes VDD < 4.5V 4.5V VDD 5.5V VSS -- VSS VSS VSS VSS VSS VSS VSS VSS 0.15 VDD 0.8 0.2 VDD 0.3 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.2 VDD 0.3 0.3 V V V V V V V V V V HS, HSPLL modes RC, EC modes(1) XT, LP modes VDD < 4.5V 4.5V VDD 5.5V Min Max Units Conditions
DC CHARACTERISTICS Param No.
Sym VIL
D030 D030A D031 D032 D032A D033 D033A D033B D034
D040 D040A D041 D042 D042A D043 D043A D043B D043C D044 Note 1: 2:
3: 4:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested.
(c) 2005 Microchip Technology Inc.
DS80172C-page 7
PIC18F8720/8620/6720/6620
7. Module: Instruction Set (BTG)
In Table 24-1: PIC18FXXXX Instruction Set (page 262), the BTG instruction has been changed (change shown in bold text).
TABLE 24-1:
Mnemonic, Operands
PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
BIT-ORIENTED FILE REGISTER OPERATIONS BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
8. Module: OSCCON Register
In the OSCCON register (Register 2-1, page 25), the Reset value for the SCS bit (OSCCON<0>) was incorrectly stated as R/W-1 and has been changed to R/W-0.
9. Module: A/D Converter Characteristics
In Table 26-25: A/D Converter Characteristics (page 340), specification A40 and Note 6 have been added:
TABLE 26-25: A/D CONVERTER CHARACTERISTICS: PIC18FXXXX (INDUSTRIAL, EXTENDED) PIC18LFXX20 (INDUSTRIAL)
Param Symbol No. A01 A03 A04 A05 A06 A10 A20 A20A A21 A22 A25 A30 A40 A50 NR EIL EDL EG EOFF -- VREF VREFH VREFL VAIN ZAIN IAD IREF Characteristic Resolution Integral Linearity Error Differential Linearity Error Gain Error Offset Error Monotonicity Reference Voltage (VREFH - VREFL) Reference Voltage High Reference Voltage Low Analog Input Voltage Recommended Impedance of Analog Voltage Source A/D Current from VDD PIC18FXXXX PIC18LFXX20 1.8V 3V AVSS AVSS - 0.3V(5) AVSS - 0.3V(5) -- -- -- -- -- Min -- -- -- -- -- Typ -- -- -- -- -- guaranteed(2) -- -- -- -- -- -- 180 90 -- -- -- -- AVDD + 0.3V VREFH AVDD + 0.3V(5) 2.5 -- -- 5 150 Max 10 <1 <1 <1 <1.5 Units bit LSb LSb LSb LSb -- V V V V V k A A A A VDD 2.5V (Note 3) (Note 4) Average current during conversion. During VAIN acquisition. During A/D conversion cycle. VREF = VDD = 5.0V VREF = VDD = 5.0V VREF = VDD = 5.0V VREF = VDD = 5.0V VSS VAIN VREF VDD < 3.0V VDD 3.0V Conditions
VREF Input Current (Note 1)
Note 1: 2: 3: 4: 5:
Vss VAIN VREF The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. For VDD < 2.5V, VAIN should be limited to <.5 VDD. Maximum allowed impedance for analog voltage source is 10 k. This requires higher acquisition times. IVDD - AVDDI must be <3.0V and IAVSS - VSSI must be <0.3V.
DS80172C-page 8
(c) 2005 Microchip Technology Inc.
PIC18F8720/8620/6720/6620
10. Module: Timer0 Block Diagram in 8-Bit and 16-Bit Modes
The PSA multiplexor bit values in Figures 11-1 and 11-2 do not match the text description of the Timer0 PSA bit in the T0CON register. The bit values have been corrected by swapping the values as shown below (correct values are shown in bold text):
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus FOSC/4 0 8 1 1 Sync with Internal Clocks 0 (2 TCY Delay) TMR0
RA4/T0CKI pin T0SE
Programmable Prescaler
3
T0PS2, T0PS1, T0PS0 T0CS
PSA
Set Interrupt Flag bit TMR0IF on Overflow
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
FOSC/4
0 1 1 Sync with Internal Clocks (2 TCY Delay) PSA T0PS2, T0PS1, T0PS0 T0CS 8 8 TMR0H 8 Data Bus<7:0> TMR0L TMR0 High Byte 8 Set Interrupt Flag bit TMR0IF on Overflow
RA4/T0CKI pin
Programmable Prescaler T0SE 3
0
Read TMR0L Write TMR0L
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
(c) 2005 Microchip Technology Inc.
DS80172C-page 9
PIC18F8720/8620/6720/6620
REVISION HISTORY
Rev A Document (10/2003) First revision of this document. Listed silicon issue 1 (Core - Program Memory Space), 2 (External Memory Interface), 3 (I/O Ports), 4 (A/D), 5 (DAW Instruction), 6 (External Memory Interface), 7 (MSSP - All I2C and SPI Modes) and 8 (MSSP - SPI, Slave Mode). Listed Data Sheet Clarification issue 1 (Comparator Voltage Reference), 2 (A/D), 3 (Data EEPROM), 4 (Memory), 5 (Timer0), 6 (Pin Diagrams), 7 (Voltage-Frequency Graph), 8 (A/D Converter Characteristics) and 9 (Electrical Characteristics). Rev B Document (12/2004) Updated device and revision ID information. Removed silicon issue 8 (MSSP - SPI, Slave Mode). Removed previous Data Sheet clarifications (1-6). Updated Data Sheet clarification 7 (Voltage-Frequency Graph), renumbered clarification 1 and added Data Sheet clarification 2 (Timing Diagrams and Specifications), 3 (CCP), 4 (Voltage Reference Specifications), 5 (Memory Programming Requirements), 6 (DC Characteristics), 7 (Instruction Set (BTG)), 8 (OSCCON Register), 9 (A/D Converter Characteristics) and 10 (Timer0 Block Diagram in 8-Bit and 16-Bit Modes). Rev C Document (05/2005) Added silicon issue 8 (Reset).
DS80172C-page 10
(c) 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2005 Microchip Technology Inc.
DS80172C-page 11
WORLDWIDE SALES AND SERVICE
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04/20/05
DS80172C-page 12
(c) 2005 Microchip Technology Inc.

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